The computer industry continually strives toward higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits (“IC's”). As new generations of IC products are released, their functionality increases while the number of components needed to produce them decreases.
Semiconductor devices are constructed from a silicon or gallium arsenide wafer through a process that comprises a number of deposition, masking, diffusion, etching, and implanting steps. Usually, many individual devices are constructed on the same wafer. When the devices are separated into individual rectangular units, each takes the form of an IC die. In order to interface a die with other circuitry, it is common to mount it on a leadframe or on a multi-chip module substrate that is surrounded by a number of lead fingers. Each die has bonding pads that are then individually connected in a wire-bonding operation to the leadframe's lead fingers using extremely fine gold or aluminum wires. The assemblies are then packaged by individually encapsulating them in molded plastic or ceramic bodies.
IC packaging technology has shown an increase in semiconductor chip density (the number of chips mounted on a single circuit board or substrate) that parallels the reduction in the number of components that are needed for a circuit. This results in packaging designs that are more compact, in form factors (the physical size and shape of a device) that are more compact, and in a significant increase in overall IC density. However, IC density continues to be limited by the space (or “real estate”) available for mounting individual dies on a substrate.
To further condense the packaging of individual devices, multi-chip packages have been developed in which more than one device (such as an IC die) can be included in the same package. Of importance to such complicated packaging designs are considerations of input/output lead count, heat dissipation, matching of thermal expansion and contraction between a motherboard and its attached components, costs of manufacturing, ease of integration into an automated manufacturing facility, package reliability, and easy adaptability of the package to additional packaging interfaces such as a printed circuit board (“PCB”).
In some cases, multi-chip devices can be fabricated faster and more cheaply than a corresponding single IC die that incorporates the same features and functions. Some multi-chip modules consist of a PCB substrate onto which a set of separate IC chip components is directly attached. Other multi-chip modules mount and attach multiple dies on a single leadframe. Following assembly, the multi-chip modules are then encapsulated to prevent damage or contamination. Many such multi-chip modules have greatly increased circuit density and miniaturization, improved signal propagation speed, reduced overall device size and weight, improved performance, and lowered costs—all primary goals of the computer industry.
However, such multi-chip modules can be bulky. IC package density is determined by the area required to mount a die or module on a circuit board. One method to reduce the board size of multi-chip modules is to stack the dies or chips vertically within the module or package. This increases their effective density.
Two of the common die stacking methods are: (a) larger lower die combined with a smaller upper die, and (b) so-called same-size die stacking. With the former, the dies can be very close vertically since the electrical bond pads on the perimeter of the lower die extend beyond the edges of the smaller die on top. With same-size die stacking, the upper and lower dies are spaced more vertically apart to provide sufficient clearance for the wire bonds of the lower die. Then, once the dies are mounted, gold or aluminum bond wires are attached to connect the wire bonding pads on the upper die and on the lower die with the ends of their associated leadframe lead extensions.
Other designs for mounting multiple semiconductor IC chips in a single, multi-chip package have included: a pair of IC dies mounted on opposite sides of a leadframe paddle, two chips mounted on two leadframe paddles, one chip mounted over a paddle and one below mounted on a board, an oblong chip that is rotated and attached on top of another oblong chip attached to a paddle below, one chip attached offset on top of another chip that is attached to a paddle below, one chip attached over another chip by separate spacers between it and the paddle, and various combinations thereof. Such configurations have also been extended to include three or more chips mounted together vertically in a single package.
Unfortunately, such practices for stacked and overlapping dies cause significant limitations for the wire bonding. These stacking arrangements typically entail attaching the upper die onto or immediately above the active surface of the lower die. Such stacking configurations cover or block some or all of the lateral edges of the bonding pads on the lower die. The mounted upper die thus interrupts the wire bond routing for the lower die. As a result, such upper and lower semiconductor dies cannot wire bond simultaneously and completely.
These limitations can be overcome to some extent by supporting the upper die on separate pillars that hold the dies apart at a greater distance. Unfortunately, however, such pillars require extra components and extra assembly, which causes extra material costs, increases processing times, raises assembly costs, and increases overall product costs.
Thus, despite the advantages of recent developments in semiconductor fabrication and packaging techniques, there is a continuing need for improved packaging designs, systems, and methods to enable increased semiconductor die density in multi-chip packages. A need particularly still remains for such improved stacked die structures in which all the active die pads can also be electrically interconnected to the lead fingers simultaneously. In view of the need to increase package efficiency and capacity and to reduce package thicknesses, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.